1. Field of the Invention
The present invention relates to a computing method of floating-point represented data for improving low frequency characteristics of an audio system. Generally the computing method of floating-point represented data having an exponential part and a mantissa part is requested to enhance the computing accuracy. More particularly, the present invention is intended to achieve higher computing accuracy in the case that a computing bit length of the floating-point represented data is constant in a digital signal processor.
2. Description of the Related Art
FIG. 1A is a view showing a prior art computing method of a digital filter. As shown in FIG. 1A, a conventional digital filter formed by DSP(Digital Signal Processor) includes multipliers 51, 52, 53, 54, and 55 factors of which are a.sub.0, a.sub.1, a.sub.2, b.sub.1 and b.sub.2 respectively, delay memories 56, 57, 58, and 59 for delaying a signal by a sampling time and an adder 60. The delay memory 56 receiving an input signal S.sub.i, is connected to the delay memory 57 in series and the delay memory 58 receiving an output signal S.sub.o is connected to the delay memory 59 in series. The multiplier 51 also receives the input signal S.sub.i, and the multipliers 52, 53, 54 and 55 are connected to outputs of the delay memories 56, 57, 58,and 59. The adder 60 is connected to outputs of the multipliers 51, 52, 53, 54 and 55 respectively to send the output signal S.sub.o.
FIG. 1B is a view showing architecture of DSP for realizing the computing method of FIG. 1A. As shown in the Figure, DSP includes registers 71 and 72 with a mutual m bit length, a multiplier 73 that multiplies data stored in the register 71 by data stored in the register 72 to output a computing result with n(n&gt;m) bit length, a register 74 for storing the computing result with n bit length output from the multiplier 73, an adder 75 that adds data stored in the register 74 to data that had been added therein before one sampling time, a register 76 that stores data with n bit length outputted from the adder 75, an internal bus 77 that is connected to the registers 71, 72, 74 and 76. The factors a.sub.0, a.sub.1, a.sub.2, b.sub.1 and b.sub.2 of the multipliers 51, 52, 53, 54 and 55 are input to either register 71 or 72, and, the input signal S.sub.i is input to the other register 72 or 71.
FIGS. 2A and 2B are views showing data used in the computation of FIG. 1B. The data with m bit length of FIG. 1B are shown in the FIG. 2A and the data with an (n&gt;m) bit length are shown in the FIG. 2B. These data are floating-point represented data having a sign, an exponential part and a mantissa part. In the architecture of DSP of FIG. 1B, the data of the registers 71 and 72 have a mutual m bit length respectively as shown in the FIG. 2A, while the computing result has the n bit length longer than that of register 71 etc. to secure the computing accuracy as shown in FIG. 2A. After this, m and n are replaced by definite numerical values since generality is not lost. So for example, m=25, n=31 are set as necessary.
FIG. 3 is a view showing a prior art low frequency gain characteristic of a digital filter. As shown in FIG. 3, in a low frequency range of the digital filter constituted in, FIG. 1A, said factors a.sub.0, a.sub.1, a.sub.2, b.sub.1 and b.sub.2 are determined to obtain, for example, a center frequency 50 Hz, a peak gain 12 dB and Q value 4 based on the computation of the architecture of DSP of FIG. 1B.
In the above computing method of floating-point represented data of the prior art, however, since a change in signal level is so small in the low frequency range to process signals in DSP of the audio system and does not especially appear sophisticated between the sampling times, a problem arises in that the computing process in the low frequency range can not be performed with high accuracy due to a shortage of a computing bit length in the digital signal processing. Further the reason for this problem will be described in detail below.
FIG. 4 is a view showing prior art total harmonic distortion in a low frequency range. As shown in the FIG. 4, about 0.3% distortion is caused on average in a total frequency range. Because the computing bit length is determined so that the sufficient great change in signal level is to be obtained in the high frequency range, but the computing bit length is not so great, as the change in signal level is detected in the low frequency range, since it is very small for the sampling period. For example definitely, in FIG. 1B, as the computing factors a.sub.0, a.sub.1, a.sub.2, b.sub.1 and b.sub.2 of the digital filter shown in FIG. 1A are stored in either the registers 71 or 72 having the mutual m bit length, the computing bit length of the computing factors is limited to the m bit length as shown in FIG. 2B. Further since the computing result with the n bit length is output once to the internal bus 77 with the m bit length in feedback computation, it is shortened to the m bit length. Therefore in order to enhance the computing accuracy of the floating-point represented data in a DSPLSI for general purpose, the computing bit length of the computing factors of the registers and the the data bit length must be made different individually but the bit length of the internal bus and also an accumulator for storing the computing result must be made great. This causes a large scale of hardware. Further even if the bit length of the accumulator can be made great, the data transmitted from the accumulator to other registers and memories are rounded off or approximated and are not sufficient to be processed in a low frequency range.